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1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4
5entity ram_controller is
6generic (
7ADDR_WIDTH : integer := 10; -- Address bus width (e.g., 10 bits for 1024 locations)
8DATA_WIDTH : integer := 8;  -- Data bus width (e.g., 8 bits)
9RAM_DEPTH  : integer := 1024 -- Number of memory locations
10);
11port (
12clk        : in  std_logic;
13reset      : in  std_logic;
14
15-- Interface to the CPU/Master
16write_en   : in  std_logic; -- Write enable from master
17read_en    : in  std_logic; -- Read enable from master
18address    : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
19data_in    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
20data_out   : out std_logic_vector(DATA_WIDTH-1 downto 0);
21ready      : out std_logic; -- Indicates controller is ready for next operation
22
23-- Interface to the RAM chip
24ram_addr   : out std_logic_vector(ADDR_WIDTH-1 downto 0);
25ram_data_in: out std_logic_vector(DATA_WIDTH-1 downto 0);
26ram_data_out: in  std_logic_vector(DATA_WIDTH-1 downto 0);
27ram_we     : out std_logic; -- RAM write enable
28ram_oe     : out std_logic; -- RAM output enable
29ram_cs     : out std_logic  -- RAM chip select
30);
31end entity ram_controller;
32
33architecture rtl of ram_controller is
34
35-- State machine for controlling RAM access timing
36type state_t is (S_IDLE, S_READ_SETUP, S_READ_ACCESS, S_READ_HOLD, S_WRITE_SETUP, S_WRITE_ACCESS, S_WRITE_HOLD);
37signal current_state, next_state : state_t;
38
39-- Internal signals for RAM control
40signal internal_ram_addr   : std_logic_vector(ADDR_WIDTH-1 downto 0);
41signal internal_ram_data_in: std_logic_vector(DATA_WIDTH-1 downto 0);
42signal internal_ram_we     : std_logic;
43signal internal_ram_oe     : std_logic;
44signal internal_ram_cs     : std_logic;
45
46-- Internal signals for data buffering and output
47signal read_buffer : std_logic_vector(DATA_WIDTH-1 downto 0);
48signal ready_signal  : std_logic;
49
50-- Timing parameters (adjust based on specific RAM datasheet)
51-- These represent clock cycles.
52constant T_SETUP_READ  : integer := 1; -- Setup time before read enable
53constant T_ACCESS_READ : integer := 2; -- Access time for read operation
54constant T_HOLD_READ   : integer := 1; -- Hold time after read enable
55
56constant T_SETUP_WRITE : integer := 1; -- Setup time before write enable
57constant T_ACCESS_WRITE: integer := 2; -- Access time for write operation (often same as read)
58constant T_HOLD_WRITE  : integer := 1; -- Hold time after write enable
59
60-- Timer for state transitions
61signal timer : integer range 0 to T_ACCESS_READ + T_SETUP_READ + T_HOLD_READ + 1; -- Max possible duration
62
63-- Helper function to initialize RAM interface signals
64function init_ram_signals return (std_logic_vector(ADDR_WIDTH-1 downto 0), std_logic_vector(DATA_WIDTH-1 downto 0), std_logic, std_logic, std_logic) is
65begin
66return ( (others => '0'), (others => '0'), '1', '1', '1'); -- CS=low, WE=high, OE=high (inactive)
67end function init_ram_signals;
68
69begin
70
71-- Assign internal signals to output ports
72ram_addr    <= internal_ram_addr;
73ram_data_in <= internal_ram_data_in;
74ram_we      <= internal_ram_we;
75ram_oe      <= internal_ram_oe;
76ram_cs      <= internal_ram_cs;
77ready       <= ready_signal;
78data_out    <= read_buffer;
79
80-- State Register Process
81process (clk, reset)
82begin
83if reset = '1' then
84current_state <= S_IDLE;
85timer <= 0;
86ready_signal <= '1'; -- Ready initially
87(internal_ram_addr, internal_ram_data_in, internal_ram_we, internal_ram_oe, internal_ram_cs) <= init_ram_signals();
88read_buffer <= (others => '0');
89elsif rising_edge(clk) then
90current_state <= next_state;
91ready_signal <= '0'; -- Not ready during operation
92
93-- Timer logic
94if timer > 0 then
95timer <= timer - 1;
96end if;
97
98-- RAM Interface Signal Updates (based on state transitions)
99case next_state is -- Use next_state to determine signal setup
100when S_IDLE =>
101(internal_ram_addr, internal_ram_data_in, internal_ram_we, internal_ram_oe, internal_ram_cs) <= init_ram_signals();
102read_buffer <= (others => '0'); -- Clear buffer
103ready_signal <= '1'; -- Ready when idle
104
105when S_READ_SETUP =>
106internal_ram_addr <= address;
107internal_ram_cs <= '0'; -- Chip select active
108internal_ram_oe <= '0'; -- Output enable active
109internal_ram_we <= '1'; -- Write enable inactive
110timer <= T_SETUP_READ;
111
112when S_READ_ACCESS =>
113-- Address and CS are already set from S_READ_SETUP
114-- OE and WE remain as set
115timer <= T_ACCESS_READ;
116
117when S_READ_HOLD =>
118-- Capture data from RAM
119read_buffer <= ram_data_out;
120internal_ram_oe <= '1'; -- Output enable inactive
121-- Keep CS low until hold time is met
122timer <= T_HOLD_READ;
123
124when S_WRITE_SETUP =>
125internal_ram_addr <= address;
126internal_ram_data_in <= data_in;
127internal_ram_cs <= '0'; -- Chip select active
128internal_ram_we <= '0'; -- Write enable active
129internal_ram_oe <= '1'; -- Output enable inactive
130timer <= T_SETUP_WRITE;
131
132when S_WRITE_ACCESS =>
133-- Address, Data, CS, WE are set
134timer <= T_ACCESS_WRITE;
135
136when S_WRITE_HOLD =>
137internal_ram_we <= '1'; -- Write enable inactive
138internal_ram_cs <= '1'; -- Chip select inactive
139-- Keep address and data stable until hold time is met
140timer <= T_HOLD_WRITE;
141
142when others => -- Should not happen
143(internal_ram_addr, internal_ram_data_in, internal_ram_we, internal_ram_oe, internal_ram_cs) <= init_ram_signals();
144ready_signal <= '1';
145end case;
146end if;
147end process;
148
149-- Next State Logic Process
150process (current_state, timer, read_en, write_en, reset)
151begin
152next_state <= current_state; -- Default to current state
153ready_signal <= '0'; -- Assume not ready unless explicitly set in IDLE
154
155if reset = '1' then
156next_state <= S_IDLE;
157else
158case current_state is
159when S_IDLE =>
160if read_en = '1' then
161next_state <= S_READ_SETUP;
162ready_signal <= '0'; -- Not ready during operation
163elsif write_en = '1' then
164next_state <= S_WRITE_SETUP;
165ready_signal <= '0'; -- Not ready during operation
166else
167next_state <= S_IDLE;
168ready_signal <= '1'; -- Ready if no operation requested
169end if;
170
171when S_READ_SETUP =>
172if timer = 0 then
173next_state <= S_READ_ACCESS;
174end if;
175
176when S_READ_ACCESS =>
177if timer = 0 then
178next_state <= S_READ_HOLD;
179end if;
180
181when S_READ_HOLD =>
182if timer = 0 then
183next_state <= S_IDLE;
184end if;
185
186when S_WRITE_SETUP =>
187if timer = 0 then
188next_state <= S_WRITE_ACCESS;
189end if;
190
191when S_WRITE_ACCESS =>
192if timer = 0 then
193next_state <= S_WRITE_HOLD;
194end if;
195
196when S_WRITE_HOLD =>
197if timer = 0 then
198next_state <= S_IDLE;
199end if;
200
201when others => -- Should not happen
202next_state <= S_IDLE;
203end case;
204end if;
205end process;
206
207-- Edge Case: Address out of bounds (if RAM_DEPTH is less than 2^ADDR_WIDTH)
208-- This implementation assumes the address is always valid for the RAM_DEPTH.
209-- A real-world controller might add checks here.
210
211-- Edge Case: Simultaneous read and write requests.
212-- The current logic prioritizes read if both read_en and write_en are high.
213-- This priority can be adjusted by modifying the S_IDLE state transitions.
214
215-- Edge Case: RAM timing parameters.
216-- The T_SETUP, T_ACCESS, T_HOLD parameters are critical.
217-- They must be derived from the specific RAM datasheet.
218-- Incorrect values will lead to read/write errors.
219
220end architecture rtl;

Algorithm description viewbox

VHDL Memory Controller for Simple RAM Access

Algorithm description:

This VHDL code implements a synchronous RAM controller designed to interface with an external Static Random Access Memory (SRAM) chip. It manages read and write operations by generating the necessary control signals (chip select, write enable, output enable) and timing them correctly according to typical SRAM access requirements.

Algorithm explanation:

The controller utilizes a finite state machine (FSM) to sequence through the phases of a read or write operation. States like `S_READ_SETUP`, `S_READ_ACCESS`, and `S_READ_HOLD` define the timing for reading data, ensuring address and control signals are stable for the required durations. Similarly, write operations are managed through `S_WRITE_SETUP`, `S_WRITE_ACCESS`, and `S_WRITE_HOLD` states. A timer within the FSM controls the duration of each state, based on timing parameters derived from the RAM's datasheet. The `ready` output signal indicates when the controller is available for a new command. This design abstracts the complex timing of memory access, providing a simpler interface to a processor or other master device. It handles basic edge cases like simultaneous read/write requests by prioritizing reads.

Pseudocode:

Define states: IDLE, READ_SETUP, READ_ACCESS, READ_HOLD, WRITE_SETUP, WRITE_ACCESS, WRITE_HOLD.
Define timing constants for setup, access, and hold times for read/write.
Initialize controller to IDLE state, ready signal high, RAM control signals inactive.
On rising edge of clock:
  Update current_state to next_state.
  If in IDLE state:
    If read_en is high, transition to READ_SETUP, set ready to low.
    Else if write_en is high, transition to WRITE_SETUP, set ready to low.
    Else, remain in IDLE, set ready to high.
  If in READ_SETUP state:
    Set address, CS low, OE low, WE high. Start timer for READ_SETUP duration.
    If timer expires, transition to READ_ACCESS.
  If in READ_ACCESS state:
    Keep signals stable. Start timer for READ_ACCESS duration.
    If timer expires, transition to READ_HOLD.
  If in READ_HOLD state:
    Capture data from RAM into read_buffer. Keep signals stable. Start timer for READ_HOLD duration.
    If timer expires, transition to IDLE.
  If in WRITE_SETUP state:
    Set address, data_in, CS low, WE low, OE high. Start timer for WRITE_SETUP duration.
    If timer expires, transition to WRITE_ACCESS.
  If in WRITE_ACCESS state:
    Keep signals stable. Start timer for WRITE_ACCESS duration.
    If timer expires, transition to WRITE_HOLD.
  If in WRITE_HOLD state:
    Keep signals stable. Start timer for WRITE_HOLD duration.
    If timer expires, transition to IDLE.
Assign output signals (ram_addr, ram_data_in, ram_we, ram_oe, ram_cs, data_out, ready) based on current state and internal signals.

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VHDL Specialist (vhdl)

VHDL Bitonic Sort Network Generator

Difficulty: writing: 6; length: 10
Popularity: 0
Created: 2026-01-26 14:02 UTC
Published: 2026-01-26 16:39 UTC
Author: Damian

#VHDL #Bitonic Sort #Parallel Algorithms #Hardware Design #Recursion #Sorting Networks #FPGA

goal: Generate a VHDL module for a parameterized bitonic sort network. input: data_array_t (N elements, power of 2), dir (sort direction) output: data_array_t (sorted)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package bitonic_sort_pkg is -- Generic for the number of elements to sort (must be a power of 2). -- For example, N=8 means sorting 8 elements. constant N : integer := 8; -- Type for the data elements being sort...

Description Algorithm

This VHDL package defines a parameterized bitonic sort network generator. A bitonic sort network is a parallel sorting algorithm that uses a fixed number of comparators arranged in stages to sort data. It's particularly...

Explanation

The bitonic sort algorithm works by first creating a bitonic sequence from the input data and then repeatedly merging these bitonic sequences until the entire array is sorted. A bitonic sequence is a sequence that is either monotonically increasing or decreasing, or it can be split into two halves, one bitonic increasing and the other bitonic decreasing, such that the elements in the first half are all less than or equal to the elements in the second half. The `generate_bitonic_sequence` procedure recursively builds such a sequence. It splits the input into two halves, recursively sorts them into bitonic sequences (one ascending, one descending), and then merges them. The `generate_bitonic_merge` procedure takes two bitonic sequences and merges them into a single sorted sequence by applying compare-and-swap operations. The `generate_bitonic_sort_network` procedure orchestrates the entire process, first calling `generate_bitonic_sequence` and then iteratively calling `generate_bitonic_merge` for increasing merge sizes until the entire array is sorted. The time complexity of a bitonic sort network for N elements is O(N log^2 N), and its space complexity is O(N log N) for the network structure itself. Edge cases include the base case of N=2, which is handled directly by a compare-swap. The recursive structure ensures correctness by maintaining the bitonic property at each step and progressively reducing the disorder until full sorting is achieved.

Pseudocode

PACKAGE bitonic_sort_pkg IS CONSTANT N : integer -- Number of elements (power of 2) TYPE data_t IS UNSIGNED(31 DOWNTO 0) TYPE data_array_t IS ARRAY(0 TO N-1) OF data_t PROCEDURE generate_bitonic_sort_network(input_data :...

Published

VHDL Specialist (vhdl)

VHDL Memory Controller for Simple RAM Access

Difficulty: writing: 8; length: 10
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #memory controller #sram #timing #state machine #digital design

goal: Implement a synchronous RAM controller in VHDL. input: clk, reset, write_en, read_en, address, data_in output: data_out, ready, ram_addr, ram_data_in, ram_we, ram_oe, ram_cs

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram_controller is generic ( ADDR_WIDTH : integer := 10; -- Address bus width (e.g., 10 bits for 1024 locations) DATA_WIDTH : integer := 8; -- Data bus width (e.g., 8 bits) RAM_DEPTH : integer := 1024 -- N...

Description Algorithm

This VHDL code implements a synchronous RAM controller designed to interface with an external Static Random Access Memory (SRAM) chip. It manages read and write operations by generating the necessary control signals (chi...

Explanation

The controller utilizes a finite state machine (FSM) to sequence through the phases of a read or write operation. States like `S_READ_SETUP`, `S_READ_ACCESS`, and `S_READ_HOLD` define the timing for reading data, ensuring address and control signals are stable for the required durations. Similarly, write operations are managed through `S_WRITE_SETUP`, `S_WRITE_ACCESS`, and `S_WRITE_HOLD` states. A timer within the FSM controls the duration of each state, based on timing parameters derived from the RAM's datasheet. The `ready` output signal indicates when the controller is available for a new command. This design abstracts the complex timing of memory access, providing a simpler interface to a processor or other master device. It handles basic edge cases like simultaneous read/write requests by prioritizing reads.

Pseudocode

Define states: IDLE, READ_SETUP, READ_ACCESS, READ_HOLD, WRITE_SETUP, WRITE_ACCESS, WRITE_HOLD. Define timing constants for setup, access, and hold times for read/write. Initialize controller to IDLE state, ready signal...

Published

VHDL Specialist (vhdl)

VHDL UART Transmitter Core

Difficulty: writing: 4; length: 10
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #uart #serial communication #transmitter #embedded systems #protocol

goal: Implement a UART transmitter core in VHDL. input: clk, reset, tx_byte, tx_start output: tx_serial, tx_busy

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity uart_tx is generic ( BAUD_RATE : integer := 9600; -- Desired baud rate (bits per second) CLOCK_FREQ : integer := 50_000_000; -- System clock frequency (Hz) DATA_BITS : integer := 8; -- Number of data bits...

Description Algorithm

This VHDL code implements a UART (Universal Asynchronous Receiver/Transmitter) transmitter core. It serializes a byte of data, adding start, parity (optional), and stop bits, and outputs it serially at a specified baud r...

Explanation

The UART transmitter uses a state machine to manage the transmission process. It first waits in an `S_IDLE` state. When `tx_start` is asserted, it loads the data byte, calculates parity if enabled, and enters `S_START_BIT` to transmit the low start bit. It then proceeds through `S_DATA_BITS` to send each data bit, followed by `S_PARITY_BIT` (if enabled), and finally `S_STOP_BITS` to send one or two high stop bits. A timer (`bit_timer`) synchronized to the system clock generates the precise timing for each bit period, calculated based on the `BAUD_RATE` and `CLOCK_FREQ`. The `tx_busy` signal indicates when a transmission is active. This design simplifies serial data transmission by handling the bit-level formatting and timing.

Pseudocode

Define states: IDLE, START_BIT, DATA_BITS, PARITY_BIT, STOP_BITS, BUSY. Calculate CYCLES_PER_BIT based on CLOCK_FREQ and BAUD_RATE. Initialize state to IDLE, tx_serial to '1' (high), busy to '0'. On rising edge of clock:...

Published

VHDL Specialist (vhdl)

VHDL Simple FSM for Traffic Light Controller

Difficulty: writing: 5; length: 8
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #fsm #traffic light #sequential logic #state machine #embedded systems

goal: Implement a VHDL finite state machine for a traffic light controller. input: clk (clock), reset (synchronous reset), enable (timer enable) output: light_out (3-bit vector for Red, Yellow, Green LEDs)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; entity traffic_light_fsm is port ( clk : in std_logic; reset : in std_logic; enable : in std_logic; light_out : out std_logic_vector(2 downto 0) -- R, Y, G ); end entity traffic_light_fsm; architecture behavioral of traffic_light_fsm is...

Description Algorithm

This VHDL code implements a finite state machine (FSM) for a basic traffic light controller. It cycles through Red, Yellow, and Green states, with each state having a defined duration controlled by a timer. This is a fun...

Explanation

The FSM uses three states: S_RED, S_YELLOW, and S_GREEN. A timer mechanism controls the duration of each state. When the timer reaches zero (or one, depending on implementation detail), the FSM transitions to the next state. The output logic maps the current state to the appropriate LED signals (Red, Yellow, Green). The reset signal initializes the FSM to the S_RED state. Edge cases include ensuring the timer correctly resets for each new state and handling any unexpected states by defaulting to S_RED. The correctness relies on the deterministic state transitions and the accurate decrementing of the timer.

Pseudocode

Define states: RED, YELLOW, GREEN. Define constants for state durations. Initialize current_state to RED and timer to RED_DURATION. On rising edge of clock: If reset is active: Set current_state to RED. Set timer to RED_...

Published

VHDL Specialist (vhdl)

VHDL Pipeline Register for Data Path Optimization

Difficulty: writing: 9; length: 6
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #pipeline #optimization #register #digital design #hardware

goal: Implement a generic pipeline register stage in VHDL. input: clk (clock), reset (synchronous reset), enable (register enable), data_in (input data ports) output: data_out (registered output data ports)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pipeline_register_stage is generic ( DATA_WIDTH : integer := 8; -- Width of the data bus NUM_PORTS : integer := 2 -- Number of parallel data ports ); port ( clk : in std_logic; reset : in std_logic; enabl...

Description Algorithm

This VHDL code defines a generic pipeline register stage, a fundamental component in optimizing digital hardware designs by breaking down complex operations into smaller, sequential stages. Each stage holds intermediate...

Explanation

The `pipeline_register_stage` entity is parameterized by `DATA_WIDTH` and `NUM_PORTS` to be flexible. On each rising edge of the clock, if `enable` is asserted, the input data (`data_in`) is captured into internal signals (`internal_data`). If `enable` is de-asserted, the `internal_data` retains its previous value, effectively stalling the pipeline stage. A synchronous reset initializes all internal data to '0' using a helper function. This design ensures that data is passed from one clock cycle to the next, enabling parallel execution of operations across different pipeline stages. The primary benefit is increased clock frequency and throughput, at the cost of increased latency.

Pseudocode

Define generic parameters for DATA_WIDTH and NUM_PORTS. Declare input ports: clk, reset, enable, data_in (array of std_logic_vectors). Declare output ports: data_out (array of std_logic_vectors). Declare internal signals...

Published

VHDL Specialist (vhdl)

VHDL Clock Domain Crossing (CDC) Synchronizer

Difficulty: writing: 7; length: 6
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #cdc #synchronizer #metastability #digital design #fpga

goal: Implement a two-stage synchronizer for Clock Domain Crossing in VHDL. input: clk_fast (destination clock), reset_fast (destination reset), data_slow (input from source domain) output: data_fast (synchronized output in destination domain)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; entity cdc_synchronizer is generic ( ASYNC_RESET : boolean := true -- Set to false for synchronous reset ); port ( clk_fast : in std_logic; -- Clock of the destination domain reset_fast : in std_logic; -- Reset for the destination domain...

Description Algorithm

This VHDL code implements a two-stage synchronizer, a common technique for Clock Domain Crossing (CDC). It takes a signal from a slower clock domain and reliably transfers it to a faster clock domain. This is essential i...

Explanation

The synchronizer uses two flip-flops clocked by the destination (fast) clock. The first flip-flop samples the input signal from the source (slow) domain. If the input signal changes near the clock edge of the fast clock, the first flip-flop might enter a metastable state. The second flip-flop, clocked by the same fast clock, samples the output of the first flip-flop. This second stage has a high probability of resolving the metastable state to a stable '0' or '1' by the time it is sampled. The probability of metastability propagating is significantly reduced. Reset logic is included for initialization. The use of a generic allows for either asynchronous or synchronous reset.

Pseudocode

Define two registers, sync_reg1 and sync_reg2, clocked by clk_fast. Apply reset logic to both registers. In the first process (sensitive to clk_fast and reset_fast): If reset is active, sync_reg1 <= '0'. Else, sync_reg1...

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