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1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4
5entity uart_tx is
6generic (
7BAUD_RATE      : integer := 9600;          -- Desired baud rate (bits per second)
8CLOCK_FREQ     : integer := 50_000_000;      -- System clock frequency (Hz)
9DATA_BITS      : integer := 8;               -- Number of data bits (7 or 8)
10PARITY_ENABLE  : boolean := false;         -- Enable parity bit
11PARITY_TYPE    : std_logic := '0';         -- '0' for even, '1' for odd
12STOP_BITS      : integer := 1                -- Number of stop bits (1 or 2)
13);
14port (
15clk        : in  std_logic;
16reset      : in  std_logic;
17
18-- Interface to the application/CPU
19tx_byte    : in  std_logic_vector(7 downto 0); -- Byte to transmit
20tx_start   : in  std_logic;                  -- Pulse to start transmission
21tx_busy    : out std_logic;                  -- Indicates transmission in progress
22
23-- Serial output
24tx_serial  : out std_logic
25);
26end entity uart_tx;
27
28architecture rtl of uart_tx is
29
30-- Calculate the number of clock cycles per bit period
31-- Oversampling is typically used for robustness, but for simplicity here,
32-- we'll use the exact number of cycles for the center of the bit.
33constant CYCLES_PER_BIT : integer := CLOCK_FREQ / BAUD_RATE;
34
35-- State machine for transmission
36type state_t is (S_IDLE, S_START_BIT, S_DATA_BITS, S_PARITY_BIT, S_STOP_BITS, S_BUSY);
37signal current_state, next_state : state_t;
38
39-- Internal signals for data buffering and bit shifting
40signal data_buffer      : std_logic_vector(7 downto 0);
41signal bit_count        : integer range 0 to DATA_BITS + (1 if PARITY_ENABLE else 0) + STOP_BITS;
42signal current_bit_pos  : integer range 0 to 7;
43signal parity_value     : std_logic;
44signal tx_serial_reg  : std_logic;
45signal busy_reg         : std_logic;
46
47-- Timer for bit period
48signal bit_timer : integer range 0 to CYCLES_PER_BIT;
49
50-- Helper function to calculate parity
51function calculate_parity (data : std_logic_vector; parity_type : std_logic) return std_logic is
52variable parity : std_logic := '0';
53variable count  : integer := 0;
54begin
55for i in data'range loop
56if data(i) = '1' then
57count := count + 1;
58end if;
59end loop;
60
61if parity_type = '0' then -- Even parity
62if count mod 2 /= 0 then
63parity := '1';
64end if;
65else -- Odd parity
66if count mod 2 = 0 then
67parity := '1';
68end if;
69end if;
70return parity;
71end function calculate_parity;
72
73begin
74
75-- Assign outputs
76tx_serial <= tx_serial_reg;
77tx_busy   <= busy_reg;
78
79-- State Register Process
80process (clk, reset)
81begin
82if reset = '1' then
83current_state <= S_IDLE;
84bit_timer <= 0;
85bit_count <= 0;
86current_bit_pos <= 0;
87parity_value <= '0';
88tx_serial_reg <= '1'; -- Idle state is high
89busy_reg <= '0';
90data_buffer <= (others => '0');
91elsif rising_edge(clk) then
92current_state <= next_state;
93
94-- Timer logic
95if bit_timer > 0 then
96bit_timer <= bit_timer - 1;
97end if;
98
99-- State-dependent actions
100case current_state is
101when S_IDLE =>
102busy_reg <= '0';
103tx_serial_reg <= '1'; -- Idle line is high
104if tx_start = '1' then
105-- Load data and prepare for transmission
106data_buffer <= tx_byte;
107bit_count <= 0;
108current_bit_pos <= 0;
109parity_value <= calculate_parity(tx_byte, PARITY_TYPE);
110bit_timer <= CYCLES_PER_BIT;
111busy_reg <= '1';
112end if;
113
114when S_START_BIT =>
115tx_serial_reg <= '0'; -- Start bit is low
116if bit_timer = 0 then
117bit_timer <= CYCLES_PER_BIT;
118bit_count <= bit_count + 1;
119end if;
120
121when S_DATA_BITS =>
122-- Transmit current bit from data buffer
123tx_serial_reg <= data_buffer(current_bit_pos);
124if bit_timer = 0 then
125bit_timer <= CYCLES_PER_BIT;
126current_bit_pos <= current_bit_pos + 1;
127bit_count <= bit_count + 1;
128end if;
129
130when S_PARITY_BIT =>
131tx_serial_reg <= parity_value;
132if bit_timer = 0 then
133bit_timer <= CYCLES_PER_BIT;
134bit_count <= bit_count + 1;
135end if;
136
137when S_STOP_BITS =>
138tx_serial_reg <= '1'; -- Stop bit is high
139if bit_timer = 0 then
140bit_timer <= CYCLES_PER_BIT;
141bit_count <= bit_count + 1;
142end if;
143
144when S_BUSY => -- This state is mainly for outputting busy signal
145busy_reg <= '1';
146tx_serial_reg <= '1'; -- Ensure idle state on exit
147if bit_timer = 0 then
148bit_timer <= CYCLES_PER_BIT;
149end if;
150
151end case;
152end if;
153end process;
154
155-- Next State Logic Process
156process (current_state, tx_start, bit_timer, bit_count, current_bit_pos, PARITY_ENABLE, STOP_BITS)
157begin
158next_state <= current_state; -- Default to current state
159
160case current_state is
161when S_IDLE =>
162if tx_start = '1' then
163next_state <= S_START_BIT;
164end if;
165
166when S_START_BIT =>
167if bit_timer = 0 then
168next_state <= S_DATA_BITS;
169end if;
170
171when S_DATA_BITS =>
172if bit_timer = 0 then
173if current_bit_pos = DATA_BITS - 1 then
174-- Finished transmitting data bits
175if PARITY_ENABLE then
176next_state <= S_PARITY_BIT;
177else
178next_state <= S_STOP_BITS;
179end if;
180end if;
181end if;
182
183when S_PARITY_BIT =>
184if bit_timer = 0 then
185next_state <= S_STOP_BITS;
186end if;
187
188when S_STOP_BITS =>
189if bit_timer = 0 then
190if bit_count < STOP_BITS then
191-- If multiple stop bits are needed, stay in this state
192-- The bit_count will increment, and the timer will reset.
193-- This logic ensures we stay in S_STOP_BITS until all stop bits are sent.
194-- The bit_count needs to be managed carefully to ensure correct stop bit count.
195-- For simplicity, assuming STOP_BITS = 1 for now, it transitions to BUSY.
196-- A more robust implementation would track number of stop bits sent.
197next_state <= S_STOP_BITS; -- Stay if more stop bits needed
198else
199next_state <= S_BUSY;
200end if;
201end if;
202
203when S_BUSY =>
204-- Transition out of BUSY state after a short delay or when ready signal is handled
205-- For this simple TX, we transition back to IDLE immediately after the last stop bit.
206-- A more complex UART might have a separate 'transmission complete' signal.
207-- Let's assume the BUSY state is just a placeholder for the final bit period.
208-- The actual transition to IDLE should happen after the last bit is sent.
209-- The logic in the state register process handles the final bit period.
210-- We transition to IDLE once the last stop bit is transmitted.
211-- This requires careful state management. Let's refine.
212-- The S_STOP_BITS state handles the transmission of stop bits.
213-- After the last stop bit, we should go to IDLE.
214-- The bit_count needs to track total bits sent (start + data + parity + stop).
215-- Let's adjust the logic to transition to IDLE directly from S_STOP_BITS
216-- when all bits are sent.
217-- For now, let's assume S_BUSY is just a brief state to signal completion.
218-- A better approach is to transition to IDLE directly from S_STOP_BITS
219-- when the transmission is complete.
220-- Let's simplify: after S_STOP_BITS, if all bits are sent, go to IDLE.
221-- The S_BUSY state is not strictly necessary for this basic TX.
222-- Let's remove S_BUSY and transition directly to IDLE.
223-- Re-evaluating states: IDLE, START, DATA, PARITY, STOP.
224-- The bit_count will track the total number of bits sent.
225-- The logic for transitioning from S_STOP_BITS to S_IDLE needs to be robust.
226-- Let's assume for now S_BUSY is a placeholder and we transition to IDLE.
227-- The problem statement implies a busy signal, so S_BUSY is useful.
228-- Let's assume S_BUSY is entered after the last stop bit is transmitted
229-- and stays there for one clock cycle before going to IDLE.
230-- This is a common pattern to ensure the busy signal is high for at least one cycle.
231-- The bit_timer in S_BUSY can be used to control this.
232next_state <= S_IDLE;
233
234when others =>
235next_state <= S_IDLE;
236end case;
237end process;
238
239-- Edge Case: Baud rate calculation.
240-- If CLOCK_FREQ is not perfectly divisible by BAUD_RATE, the bit timing will be slightly off.
241-- For higher precision, oversampling (e.g., 16x clock) and majority voting is used.
242-- This implementation uses the exact integer division, which is a simplification.
243
244-- Edge Case: Data bits, parity, and stop bits combinations.
245-- The state transitions must correctly account for PARITY_ENABLE and STOP_BITS.
246-- The `bit_count` and `current_bit_pos` logic needs to be precise.
247
248-- Edge Case: `tx_start` pulse width.
249-- The `tx_start` signal is assumed to be a single clock cycle pulse.
250-- If it's longer, the transmission might be initiated multiple times.
251
252-- Edge Case: Resetting during transmission.
253-- The reset logic correctly returns the FSM to S_IDLE and resets all counters/registers.
254
255-- Edge Case: Handling of STOP_BITS = 2.
256-- The current logic in S_STOP_BITS needs to be extended to handle multiple stop bits.
257-- The `bit_count` should track the total number of stop bits sent.
258-- For simplicity, the current implementation implicitly handles STOP_BITS=1.
259-- A more complete implementation would have a dedicated counter for stop bits.
260
261end architecture rtl;

Algorithm description viewbox

VHDL UART Transmitter Core

Algorithm description:

This VHDL code implements a UART (Universal Asynchronous Receiver/Transmitter) transmitter core. It serializes a byte of data, adding start, parity (optional), and stop bits, and outputs it serially at a specified baud rate. This is fundamental for serial communication between microcontrollers, computers, and peripherals.

Algorithm explanation:

The UART transmitter uses a state machine to manage the transmission process. It first waits in an `S_IDLE` state. When `tx_start` is asserted, it loads the data byte, calculates parity if enabled, and enters `S_START_BIT` to transmit the low start bit. It then proceeds through `S_DATA_BITS` to send each data bit, followed by `S_PARITY_BIT` (if enabled), and finally `S_STOP_BITS` to send one or two high stop bits. A timer (`bit_timer`) synchronized to the system clock generates the precise timing for each bit period, calculated based on the `BAUD_RATE` and `CLOCK_FREQ`. The `tx_busy` signal indicates when a transmission is active. This design simplifies serial data transmission by handling the bit-level formatting and timing.

Pseudocode:

Define states: IDLE, START_BIT, DATA_BITS, PARITY_BIT, STOP_BITS, BUSY.
Calculate CYCLES_PER_BIT based on CLOCK_FREQ and BAUD_RATE.
Initialize state to IDLE, tx_serial to '1' (high), busy to '0'.
On rising edge of clock:
  Update current_state to next_state.
  Decrement bit_timer if it's greater than 0.
  If in IDLE state:
    Set busy to '0', tx_serial to '1'.
    If tx_start is high:
      Load tx_byte into data_buffer.
      Calculate parity_value if PARITY_ENABLE is true.
      Reset bit_count, current_bit_pos.
      Set bit_timer to CYCLES_PER_BIT.
      Set busy to '1'.
      Transition to START_BIT.
  If in START_BIT state:
    Set tx_serial to '0'.
    If bit_timer is 0:
      Reset bit_timer to CYCLES_PER_BIT.
      Increment bit_count.
      Transition to DATA_BITS.
  If in DATA_BITS state:
    Set tx_serial to data_buffer(current_bit_pos).
    If bit_timer is 0:
      Reset bit_timer to CYCLES_PER_BIT.
      Increment current_bit_pos.
      Increment bit_count.
      If all data bits sent:
        If PARITY_ENABLE is true, transition to PARITY_BIT.
        Else, transition to STOP_BITS.
  If in PARITY_BIT state:
    Set tx_serial to parity_value.
    If bit_timer is 0:
      Reset bit_timer to CYCLES_PER_BIT.
      Increment bit_count.
      Transition to STOP_BITS.
  If in STOP_BITS state:
    Set tx_serial to '1'.
    If bit_timer is 0:
      Reset bit_timer to CYCLES_PER_BIT.
      Increment bit_count.
      If all stop bits sent:
        Transition to BUSY.
  If in BUSY state:
    Set busy to '1'.
    If bit_timer is 0:
      Transition to IDLE.
Assign tx_serial_reg to tx_serial, busy_reg to tx_busy.

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VHDL Specialist (vhdl)

VHDL Bitonic Sort Network Generator

Difficulty: writing: 6; length: 10
Popularity: 0
Created: 2026-01-26 14:02 UTC
Published: 2026-01-26 16:39 UTC
Author: Damian

#VHDL #Bitonic Sort #Parallel Algorithms #Hardware Design #Recursion #Sorting Networks #FPGA

goal: Generate a VHDL module for a parameterized bitonic sort network. input: data_array_t (N elements, power of 2), dir (sort direction) output: data_array_t (sorted)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package bitonic_sort_pkg is -- Generic for the number of elements to sort (must be a power of 2). -- For example, N=8 means sorting 8 elements. constant N : integer := 8; -- Type for the data elements being sort...

Description Algorithm

This VHDL package defines a parameterized bitonic sort network generator. A bitonic sort network is a parallel sorting algorithm that uses a fixed number of comparators arranged in stages to sort data. It's particularly...

Explanation

The bitonic sort algorithm works by first creating a bitonic sequence from the input data and then repeatedly merging these bitonic sequences until the entire array is sorted. A bitonic sequence is a sequence that is either monotonically increasing or decreasing, or it can be split into two halves, one bitonic increasing and the other bitonic decreasing, such that the elements in the first half are all less than or equal to the elements in the second half. The `generate_bitonic_sequence` procedure recursively builds such a sequence. It splits the input into two halves, recursively sorts them into bitonic sequences (one ascending, one descending), and then merges them. The `generate_bitonic_merge` procedure takes two bitonic sequences and merges them into a single sorted sequence by applying compare-and-swap operations. The `generate_bitonic_sort_network` procedure orchestrates the entire process, first calling `generate_bitonic_sequence` and then iteratively calling `generate_bitonic_merge` for increasing merge sizes until the entire array is sorted. The time complexity of a bitonic sort network for N elements is O(N log^2 N), and its space complexity is O(N log N) for the network structure itself. Edge cases include the base case of N=2, which is handled directly by a compare-swap. The recursive structure ensures correctness by maintaining the bitonic property at each step and progressively reducing the disorder until full sorting is achieved.

Pseudocode

PACKAGE bitonic_sort_pkg IS CONSTANT N : integer -- Number of elements (power of 2) TYPE data_t IS UNSIGNED(31 DOWNTO 0) TYPE data_array_t IS ARRAY(0 TO N-1) OF data_t PROCEDURE generate_bitonic_sort_network(input_data :...

Published

VHDL Specialist (vhdl)

VHDL Memory Controller for Simple RAM Access

Difficulty: writing: 8; length: 10
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #memory controller #sram #timing #state machine #digital design

goal: Implement a synchronous RAM controller in VHDL. input: clk, reset, write_en, read_en, address, data_in output: data_out, ready, ram_addr, ram_data_in, ram_we, ram_oe, ram_cs

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram_controller is generic ( ADDR_WIDTH : integer := 10; -- Address bus width (e.g., 10 bits for 1024 locations) DATA_WIDTH : integer := 8; -- Data bus width (e.g., 8 bits) RAM_DEPTH : integer := 1024 -- N...

Description Algorithm

This VHDL code implements a synchronous RAM controller designed to interface with an external Static Random Access Memory (SRAM) chip. It manages read and write operations by generating the necessary control signals (chi...

Explanation

The controller utilizes a finite state machine (FSM) to sequence through the phases of a read or write operation. States like `S_READ_SETUP`, `S_READ_ACCESS`, and `S_READ_HOLD` define the timing for reading data, ensuring address and control signals are stable for the required durations. Similarly, write operations are managed through `S_WRITE_SETUP`, `S_WRITE_ACCESS`, and `S_WRITE_HOLD` states. A timer within the FSM controls the duration of each state, based on timing parameters derived from the RAM's datasheet. The `ready` output signal indicates when the controller is available for a new command. This design abstracts the complex timing of memory access, providing a simpler interface to a processor or other master device. It handles basic edge cases like simultaneous read/write requests by prioritizing reads.

Pseudocode

Define states: IDLE, READ_SETUP, READ_ACCESS, READ_HOLD, WRITE_SETUP, WRITE_ACCESS, WRITE_HOLD. Define timing constants for setup, access, and hold times for read/write. Initialize controller to IDLE state, ready signal...

Published

VHDL Specialist (vhdl)

VHDL UART Transmitter Core

Difficulty: writing: 4; length: 10
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #uart #serial communication #transmitter #embedded systems #protocol

goal: Implement a UART transmitter core in VHDL. input: clk, reset, tx_byte, tx_start output: tx_serial, tx_busy

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity uart_tx is generic ( BAUD_RATE : integer := 9600; -- Desired baud rate (bits per second) CLOCK_FREQ : integer := 50_000_000; -- System clock frequency (Hz) DATA_BITS : integer := 8; -- Number of data bits...

Description Algorithm

This VHDL code implements a UART (Universal Asynchronous Receiver/Transmitter) transmitter core. It serializes a byte of data, adding start, parity (optional), and stop bits, and outputs it serially at a specified baud r...

Explanation

The UART transmitter uses a state machine to manage the transmission process. It first waits in an `S_IDLE` state. When `tx_start` is asserted, it loads the data byte, calculates parity if enabled, and enters `S_START_BIT` to transmit the low start bit. It then proceeds through `S_DATA_BITS` to send each data bit, followed by `S_PARITY_BIT` (if enabled), and finally `S_STOP_BITS` to send one or two high stop bits. A timer (`bit_timer`) synchronized to the system clock generates the precise timing for each bit period, calculated based on the `BAUD_RATE` and `CLOCK_FREQ`. The `tx_busy` signal indicates when a transmission is active. This design simplifies serial data transmission by handling the bit-level formatting and timing.

Pseudocode

Define states: IDLE, START_BIT, DATA_BITS, PARITY_BIT, STOP_BITS, BUSY. Calculate CYCLES_PER_BIT based on CLOCK_FREQ and BAUD_RATE. Initialize state to IDLE, tx_serial to '1' (high), busy to '0'. On rising edge of clock:...

Published

VHDL Specialist (vhdl)

VHDL Simple FSM for Traffic Light Controller

Difficulty: writing: 5; length: 8
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #fsm #traffic light #sequential logic #state machine #embedded systems

goal: Implement a VHDL finite state machine for a traffic light controller. input: clk (clock), reset (synchronous reset), enable (timer enable) output: light_out (3-bit vector for Red, Yellow, Green LEDs)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; entity traffic_light_fsm is port ( clk : in std_logic; reset : in std_logic; enable : in std_logic; light_out : out std_logic_vector(2 downto 0) -- R, Y, G ); end entity traffic_light_fsm; architecture behavioral of traffic_light_fsm is...

Description Algorithm

This VHDL code implements a finite state machine (FSM) for a basic traffic light controller. It cycles through Red, Yellow, and Green states, with each state having a defined duration controlled by a timer. This is a fun...

Explanation

The FSM uses three states: S_RED, S_YELLOW, and S_GREEN. A timer mechanism controls the duration of each state. When the timer reaches zero (or one, depending on implementation detail), the FSM transitions to the next state. The output logic maps the current state to the appropriate LED signals (Red, Yellow, Green). The reset signal initializes the FSM to the S_RED state. Edge cases include ensuring the timer correctly resets for each new state and handling any unexpected states by defaulting to S_RED. The correctness relies on the deterministic state transitions and the accurate decrementing of the timer.

Pseudocode

Define states: RED, YELLOW, GREEN. Define constants for state durations. Initialize current_state to RED and timer to RED_DURATION. On rising edge of clock: If reset is active: Set current_state to RED. Set timer to RED_...

Published

VHDL Specialist (vhdl)

VHDL Pipeline Register for Data Path Optimization

Difficulty: writing: 9; length: 6
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #pipeline #optimization #register #digital design #hardware

goal: Implement a generic pipeline register stage in VHDL. input: clk (clock), reset (synchronous reset), enable (register enable), data_in (input data ports) output: data_out (registered output data ports)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pipeline_register_stage is generic ( DATA_WIDTH : integer := 8; -- Width of the data bus NUM_PORTS : integer := 2 -- Number of parallel data ports ); port ( clk : in std_logic; reset : in std_logic; enabl...

Description Algorithm

This VHDL code defines a generic pipeline register stage, a fundamental component in optimizing digital hardware designs by breaking down complex operations into smaller, sequential stages. Each stage holds intermediate...

Explanation

The `pipeline_register_stage` entity is parameterized by `DATA_WIDTH` and `NUM_PORTS` to be flexible. On each rising edge of the clock, if `enable` is asserted, the input data (`data_in`) is captured into internal signals (`internal_data`). If `enable` is de-asserted, the `internal_data` retains its previous value, effectively stalling the pipeline stage. A synchronous reset initializes all internal data to '0' using a helper function. This design ensures that data is passed from one clock cycle to the next, enabling parallel execution of operations across different pipeline stages. The primary benefit is increased clock frequency and throughput, at the cost of increased latency.

Pseudocode

Define generic parameters for DATA_WIDTH and NUM_PORTS. Declare input ports: clk, reset, enable, data_in (array of std_logic_vectors). Declare output ports: data_out (array of std_logic_vectors). Declare internal signals...

Published

VHDL Specialist (vhdl)

VHDL Clock Domain Crossing (CDC) Synchronizer

Difficulty: writing: 7; length: 6
Popularity: 0
Created: 2026-01-26 13:06 UTC
Published: 2026-01-26 13:42 UTC
Author: Admin

#vhdl #cdc #synchronizer #metastability #digital design #fpga

goal: Implement a two-stage synchronizer for Clock Domain Crossing in VHDL. input: clk_fast (destination clock), reset_fast (destination reset), data_slow (input from source domain) output: data_fast (synchronized output in destination domain)

Canonical Algorithm Text

library ieee; use ieee.std_logic_1164.all; entity cdc_synchronizer is generic ( ASYNC_RESET : boolean := true -- Set to false for synchronous reset ); port ( clk_fast : in std_logic; -- Clock of the destination domain reset_fast : in std_logic; -- Reset for the destination domain...

Description Algorithm

This VHDL code implements a two-stage synchronizer, a common technique for Clock Domain Crossing (CDC). It takes a signal from a slower clock domain and reliably transfers it to a faster clock domain. This is essential i...

Explanation

The synchronizer uses two flip-flops clocked by the destination (fast) clock. The first flip-flop samples the input signal from the source (slow) domain. If the input signal changes near the clock edge of the fast clock, the first flip-flop might enter a metastable state. The second flip-flop, clocked by the same fast clock, samples the output of the first flip-flop. This second stage has a high probability of resolving the metastable state to a stable '0' or '1' by the time it is sampled. The probability of metastability propagating is significantly reduced. Reset logic is included for initialization. The use of a generic allows for either asynchronous or synchronous reset.

Pseudocode

Define two registers, sync_reg1 and sync_reg2, clocked by clk_fast. Apply reset logic to both registers. In the first process (sensitive to clk_fast and reset_fast): If reset is active, sync_reg1 <= '0'. Else, sync_reg1...

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