ℹ️ Select 'Choose Exercise', or randomize 'Next Random Exercise' in selected language.

Choose Exercise:
Timer 00:00
WPM --
Score --
Acc --
Correct chars --

PLC Ladder Logic: Basic Timer with Delay

PLC Ladder Diagram (LD)

Goal -- WPM

Ready
Exercise Algorithm Area
1PROGRAM TimerLogic
2
3VAR
4Enable : BOOL;
5DelayTime : TIME := T#5s; // 5 second delay
6Output : BOOL;
7TimerRunning: BOOL;
8TimerDone : BOOL;
9END_VAR
10
11// Rung 1: Timer Enable Logic
12// If Enable is true, set TimerRunning flag.
13// If Enable is false, reset TimerRunning flag and TimerDone flag.
14
15IF Enable THEN
16TimerRunning := TRUE;
17ELSE
18TimerRunning := FALSE;
19TimerDone := FALSE;
20END_IF
21
22// Rung 2: Simulate Timer Delay
23// This rung simulates a timer. In a real PLC, a TON (Timer ON) instruction would be used.
24// For this example, we'll increment a counter and check against DelayTime.
25VAR
26ElapsedTime : INT;
27MaxTicks : INT;
28END_VAR
29
30// Assuming a PLC scan rate of 10ms for simulation purposes
31// MaxTicks = DelayTime (in ms) / ScanRate (in ms)
32// For T#5s (5000ms) and 10ms scan rate, MaxTicks = 5000 / 10 = 500
33MaxTicks := 500; // Pre-calculated for 5s delay at 10ms scan rate
34
35IF TimerRunning AND NOT TimerDone THEN
36IF ElapsedTime < MaxTicks THEN
37ElapsedTime := ElapsedTime + 1;
38ELSE
39TimerDone := TRUE;
40END_IF
41ELSE
42// Reset timer if not running or already done
43ElapsedTime := 0;
44END_IF
45
46// Rung 3: Output Logic
47// If TimerDone is true, set the Output signal.
48
49Output := TimerDone;
50
51END_PROGRAM
Algorithm description viewbox

PLC Ladder Logic: Basic Timer with Delay

Algorithm description:

This PLC Ladder Diagram program implements a basic ON-delay timer. It simulates the behavior of a timer that starts counting when an 'Enable' input signal becomes active. After a predefined delay period, an 'Output' signal is activated. If the 'Enable' signal is deactivated before the delay elapses, the timer resets, and the output remains inactive. This is commonly used in industrial control to introduce delays in sequences, such as activating a motor after a certain waiting period or delaying a signal.

Algorithm explanation:

The program simulates an ON-delay timer using basic boolean logic and integer arithmetic. The `Enable` input triggers the timing process. The `TimerRunning` flag is set when `Enable` is true, indicating the timer has started. The `ElapsedTime` variable increments with each PLC scan cycle as long as `TimerRunning` is true and `TimerDone` is false. `MaxTicks` is pre-calculated based on the desired `DelayTime` and the PLC's scan rate to represent the total number of scans needed for the delay. Once `ElapsedTime` reaches `MaxTicks`, `TimerDone` is set to true, which in turn activates the `Output`. If `Enable` goes false, `TimerRunning` and `TimerDone` are reset, effectively aborting the timing sequence. The time complexity is O(1) per scan cycle, as it performs a fixed number of operations. The space complexity is O(1) due to the fixed number of variables. Edge cases handled include resetting the timer if the enable signal is removed before the delay is complete.

Pseudocode:

PROGRAM TimerLogic
  VARIABLES:
    Enable: BOOLEAN
    DelayTime: TIME = 5 seconds
    Output: BOOLEAN
    TimerRunning: BOOLEAN
    TimerDone: BOOLEAN
    ElapsedTime: INTEGER
    MaxTicks: INTEGER

  // Assume ScanRate = 10ms
  MaxTicks = DelayTime (in ms) / ScanRate (in ms)

  // Rung 1: Timer Enable Logic
  IF Enable THEN
    TimerRunning = TRUE
  ELSE
    TimerRunning = FALSE
    TimerDone = FALSE
  END_IF

  // Rung 2: Simulate Timer Delay
  IF TimerRunning AND NOT TimerDone THEN
    IF ElapsedTime < MaxTicks THEN
      ElapsedTime = ElapsedTime + 1
    ELSE
      TimerDone = TRUE
    END_IF
  ELSE
    ElapsedTime = 0
  END_IF

  // Rung 3: Output Logic
  Output = TimerDone
END_PROGRAM